1. Field of the Invention
The present invention relates to an apparatus for testing a semiconductor integrated circuit and a method for testing the semiconductor integrated circuit, and more particularly, to an apparatus for testing a semiconductor integrated circuit that includes a plurality of semiconductor elements operating in an asynchronous manner, and a method for testing the semiconductor integrated circuit.
2. Related Art
Testing a semiconductor integrated circuit that includes resisters asynchronously operating with clocks of different frequencies and involves data transfers between a plurality of semiconductor elements is carried out by performing a simulation with the use of test vectors that are created by an engineer. Japanese Patent Application Laid-Open Publication No. 2005-182093 discloses one of those conventional testing methods.
In recent years, however, the number of clocks has increased in SoC designs, and the designs have become complicated. Therefore, the number of points at which asynchronous transfers occur (hereinafter referred to as the “asynchronous transfer points”) has increased, and the number of subject points and items to be tested has also increased. As a result, a large amount of work time is imposed on each engineer to create test vectors.
In testing a semiconductor integrated circuit that has transfer errors such as asynchronous transfers, it is necessary to carry out a test on a violation equivalent to a transfer error due to metastability, as well as a test on a simple normal operation.
To reproduce such a violation with test vectors, it is necessary to accurately grasp the timing in the semiconductor integrated circuit, and consider various combinations of clock timings provided in the test vectors and transfer data. As a result, the work time imposed on each engineer to create test vectors has been increasing.